Frequency synthesizer with pseudo-reference phase comparator

ABSTRACT

A frequency synthesizer having two feedback control loops, one employing a frequency comparator and the other including a sampling phase comparator. The device is useful in high frequency synthesis of a frequency program such as provided by a digitally programmable frequency divider.

United States Patent Margala et a1.

1 1 Sept. 30, 1975 I FREQUENCY SYNTHESIZER WITH PSEUDO-REFERENCE PHASE COMPARATOR [75] Inventors: Jean Pierre Margala; Jean Louis Roger Cassany, both of Paris. France [731 Assignee: International Standard Electric Corporation, New York. NY.

122] Filed: Feb. 25, 1974 [21] Appl. No.: 445,603

[52] US. Cl. 331/11; 307/271; 331/25;

[51] Int. Cl.'- H03B 3/04 [58] Field of Search .331/10,11, 28, 25;

[56] References Cited UNITED STATES PATENTS 3.815.042 6/1974 Maunsell et a1. 331/1 1 FOREIGN PATENTS OR APPLICATIONS 1.034.427 3/1966 United Kingdom 331/1 1 Primary li\'aminer.lohn Kominski Attorney, Agent, or Firm-William T. ONeil [57] ABSTRACT A frequency synthesizer having two feedback control loops. one employing a frequency comparator and the other including a sampling phase comparator. The device is useful in high frequency synthesis of a frequency program such as provided by a digitally programmable frequency divider.

5 Claims, 3 Drawing Figures U.S. Patent Sept. 30,1975

FREQUENCY SYNTHESIZER WITH PSEUDO-REFERENCE PHASE COMPARATOR BACKGROUND OF THE INVENTION 1. Field of the Invention v The present invention relates to a frequency synthesizer using a sampling phase comparator.

2. Description of the Prior Art 7 A known synthesizer of the type-with which this invention is concerned is basically an apparatus for generation of one of the lines of a discontinuous spectrum of predetermined stable frequencies which are multiples of a reference frequency f,,.

In the so-called direct division synthesizer, the spectrum is produced from a voltage controlled oscillator having a frequency F controlled by a voltage and divided by N in a variable ratio divider. The signal of frequency A fA N to be analyzed has its frequency and phase compared to those of a signal at a reference frequency f,; in two comparators which deliver output voltages to the VCO so as to control the oscillation frequency up to the value F, Nf the first voltage corresponding to a presetting adjustment and the second one to a fine adjustment providing the synchronization.

In synthesizers, particularly those which are used in air traffic radionavigation systems, it is necessary that, after having set the division ratio N for producing an oscillation frequency F,, Nf the frequency comparator and the associated control loop, which provide the presetting, have a very short acquisition time so as to vary, as rapidly as possible, the voltage from its initial value, defining a frequency F to the final value defining the desired frequency F Nf- In known art, usually the presetting voltage (i.e., corresponding to frequency F3) does not vary during the acquisition period in a continuous manner but does vary step by step in a discontinuous manner so that the phase comparator must relieve the frequency comparator in order to correct the frequency differences between F and F which are less than the frequency step AF [F F :5 AF).

The digital presetting of a variable ratio divider, such as effected by elements 2 and 3 in combination, or the digital control of an oscillator frequency are known techniques obvious to those skilled in this art. For various reasons, it is not recommended to reduce AF too much. Indeed, the elementary acquisition time corre sponding to the passage from division ratio N to ratio (N-l) or (N-H) is:

a fl:

may be defined which is expressed in radian frequency/volts or in radians/second/volt. Assuming the phenomena to be linear, G is:

(V being the maximum value of V Neglecting certain secondary components of the control loop, the phase comparator has a conversion slope expressed in volts/radian, where d) is the phase deviation between pulses at frequency f an fA, bOth being applied to the comparator. If the phenomena are linear,

it is possible to write:

The open-loop transfer function H of the control system; comprising, in a simplified design, the variable ratio divider VRD, the phase comparator and the control input of the VCO; may be expressed in symbolic language, using the variable p of the Laplace transform:

AF (i.e.. H T

when phenomena are linear).

In closed loop, transfer transform H is written:

G06, H H, N

' l+H,, GOG,

Considering the relation of H it is possible to say that any random variation AF of frequency F apart its balance value Nf is compressed by the control system down to a value (F according to a law:

Thus the greatest is (G,, G,/N), and the corresponding compression is most rapid and the control system is most efficient.

In general, it is known that, in a control system the open-loop gain must be as high as possible so as to obtain good stability of the controlled magnitude and to reduce noise. In the present case, when the loop gain i.e., (G G /N) is relatively high, the signal from the VCO is constituted by a very narrow line at frequency Nf without random frequency modulation.

Practically, G does not vary as a linear function of V and increases much less rapidly than V,,. Otherwise stated, the open-loop gain is substantially reduced when V increases and becomes insufficient for providing good stabilization of the F frequency. This occurs when V reaches the value (VQ That situation develops in known sampling phase comparators which operate as follows.

A reference signal at frequency f synchronizes a generator delivering (ideally) a saw-tooth voltage, that generator including. a DC source charging a capacitor of capacitance C, The signal at frequency f from the VRD opens l (at a rate 'f a memory wherein the voltage V,. is stored across the capacitor.

If the voltage generator is actually a saw-tooth generator, the instantaneous voltage E,- is proportional to time and thus to phase shift (b. But any actual source has an internal resistance of finite value p and the variation law for E is not truly linear as a function of time t or phase shift d). In fact, it is of the form of E E,, being the voltage of the DC source and 1' being the time constant p C.

The conversion slope G, is written:

As time l/f corresponds to a phase shift of 21r:

G which is at a maximum of for d) 0, reaches the minimum value.

G, may be still written as if (E /E is small enough compared to unity, the phenomena stay linear, but that is no longer true if (E /E approaches unity. G decreases to 0 in that case.

To overcome that drawback, in known techniques, E has been considerably increased so as to satisfy the condition (ES)M Such an increase of the source emf is not acceptable in many equipments. Up to now it has been assumed that the DC source has a constant value E,,. It may be also assumed that that source delivers a constant current I Then the charge law of the capacitor of capacitance C is linear as a function of time and of phase shift, and

SUMMARY OF THE INVENTION A purpose of this invention is to provide a sampling phase comparator having a rather constant conversion slope value 6,, such a value being close to the maximum value while maintaining the DC source at the same value E that it would have if the phenomena were linear.

In accordance with already adopted notations, E =(21rf r) (G results.

According to a feature of this invention, m pulses at frequency m f,; (constituting a pseudo-referencesignal) correspond to a pulse at reference frequency f those pseudo-reference pulses replacing the single pulse used in the usual prior art sampling phase comparator.

After each pulse at frequency m f capacitor C is charged during a time (l/f and the conversion slope G varies from If m is great enough, e l/m f r stays very close to l and G remains relatively constant. The maximum voltage across C is With a DC current source, the voltage across C varies linearly during a time (l/m f and reaches the value Therefore the source emf may be maintained at a value that is m times smaller than that which is necessary when the device according to this invention is not utilized.

Accordingly, the single saw-tooth corresponding to a maximum voltage from phase comparator output equal to (I /Cf is replaced by a sequence of m similar sawteeth having the same slope as the single saw-tooth and each corresponding to a maximum voltage (I /mCf The utilization of the device according to the invention has an additional advantage, namely that the output voltage (B from the phase comparator, which is applied to the VCO is in times smaller than that which is applied in usual phase comparator.

In prior art, the oscillation frequency adjustment for the VCO is effected by varying the capacitance of a varactor under the influence of E The voltage, which may be accepted by a varactor is limited and in usual cases voltage (B must be reduced by any suitable means before being applied to the varactor. On the contrary, with the device according to this invention, a suitable selection of m permits a voltage (E small enough to eliminate the need for any voltage reducer. Inprior art devices, saw-tooth voltages across the capacitor C occur at frequency f;,, the passage from one saw-tooth to the next one being achieved by shortcircuiting the capacitor of capacity C. That shortcircuit condition duration must be very short compared to I In the device according to this invention, on the other hand, the saw-tooth voltages occur at frequency mf and, during a sampling period (llf the capacitor C isshort-circuited m times. The duration of each of those short-circuit conditions is substantially shorter than that which is tolerable in prior art devices. Indeed, it is necessary to reduce to a minimum the dead times of phase scanning.

In other words, pulses at frequency mf must be very short.

Those pulses are delivered from a sharper circuit.

In known art, pulses at frequency f,; are produced by digitally dividing the highly stabilized frequency F of a rectangular signal source (F Mf by M.

According to another feature of this invention, the digital divider comprises two outputs, a division-by-M output delivering those pulses at frequency f,, which will be used in a synthesizer frequency comparator and a division-by-(M/m) output delivering pulses at frequency mf which must be processed in a shaper.

According to another feature of this invention, the shaper consists in a flip-flop provided with a priority reset input receiving rectangular singles at frequency F and a pulse input receiving pulses at frequency mf m"B (or 7).

Due to this arrangement pulses at frequency mf have, at the flip-flop output, a width less than or equal to B)- In the device described, the frequency comparison function in 5 is operative as long as |F Nf AF, whereas control by phase comparison in 10 is active as soon as F Nf l AF.

Other features of this invention will appear more clearly from the following detailed description of an embodiment, the said description being made in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a digital frequency synthesizer utilizing a sampling phase comparator according to the invention.

FIG. 2 shows details of a pulse shaper according to the invention.

FIG. 3 shows a set of waveforms for explaining the operation of the sampling phase comparator shown in FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. 1, a description of the structure and function of a device for practicing the invention will be described.

VCO oscillator 1 has a frequency F which is controlled by one or several voltages which are, for example, applied to varactors included in the tuning capacitor of the oscillating circuit.

Signals at frequency F are sent from 1 to a variable ratio frequency divider 2 having a division ratio l/N determined from a control unit 3.

Pulses, at frequency are transmitted from 2, via lines 4 and 4a, to input 5a of frequency comparator 5, whose other input 5b receives pulses at reference frequency f,,. From the output of 5, an error voltage appears which is proportional to |f f l and which is, via lead 6, applied to one of the control input la of VCO 1. 7

Frequency comparator 5 may be, for example, of the type described in U.S. Pat. No. 3,824,483.

That frequency comparator provides a presetting which leads to a frequency difference IF F less than or equal to AF.

Pulses, at reference frequency f,,, are delivered from output 7a of frequency divider 7, whose input receives signals at frequency F delivered by highly stabilized oscillator 8. Output 7a corresponds to a division ratio of Divider 7 also has an output 7b which corresponds to a division ratio (m/M). Output 712 is connected to the input of pulse shaper 9.

Shaper 9 comprises components and connections as follows:

One input of a two-input AND gate 9d receives signals from output 7b of 7.

Output 7b is also connected to a NOT gate 9a whose output is, via a delay circuit comprising resistor 9b and capacitor 90, connected to the second input of 9d. Each time a logic level l appears from output 7b, the two inputs of 9d are in condition 1, and 9d is turned on and is only turned off after a time duration which is roughly determined by the time constant of 9c and 9b.

Thus, pulses at the pseudo-reference frequency are delivered from output of 9 with the desired width.

Block 10 comprises a sampling phase comparator according to this invention.

The output of 9 is connected, through a protection resistor l l, to the base of a transistor 12 having its collector supplied, via resistor 13 of value p, by a DC source 14 having emf E The internal resistance of 14 is considered as a part of 13.

The emitter of 12 is connected to ground and capacitor 15, having a capacitance C, is connected from collector to ground.

The collector of 12 is connected to a field-effect transistor 16 phase whose drain is connected to one of the electrodes of. capacitor 17, called the memorycapacitor. The gate of 16 is connectcd, via line 44b, from the output of variable ratio divider 2 and thus receives pulses at analysis frequency The voltage across 17 is amplified in an operational amplifier 18 having a very high input impedance and very small output impedance. Amplifier 18 is followed by a low-pass filter 19 whose output is, via line 20, connected to one of the control inputs lb of VCO l. The function of 19 consists in eliminating components, at frequencies f,, and mf,,, from the error voltage delivered by 18.

Operation of circuits shown in FIG. 1

It is to be noted that transistors 12 and 16 operate as impedance switches. Considering transistor 12 for example, its emitter-collector space has a very low impedance when a pseudo-reference pulse is applied to its base, and a very high impedance between such pulses.

Thus capacitor is discharged during application of a pseudo-reference pulse to the base of 12.

The source-drain space of 16 has a very high impedance when no analysis pulse is applied to its gate, and a very low impedance when an analysis pulse is applied thereto. Thus, typically, a voltage appears across capacitor 7 which stays substantially constant between two successive analysis pulses.

During the very short duration of an analysis pulse, the voltage across 17 has the instantaneous value of the voltage across capacitor 15. The operation of the assembly shown in FIG, 1 is then as follows:

It is assumed that VCO 1 is operating at a frequency (F N f the division ratio l/N being set by means of ratio control unit 3 and variable ratio divider 2. F requency comparator 5 is rendered operative and the error voltage is, via line 6, applied to input la of VCO l and thus changes the oscillation frequency by steps each equal to AF up to F Nf s AF.

As long as that condition is extant, frequency comparator 5 remains inoperative and phase comparator 10 operates alone for slaving frequency F A to frequency Nf The waveforms shown in FIG. 3, which illustrate variations of voltages E across capacitor 15 and V across memory capacitor 17, versus time, make it possible to understand the operation of phase comparator 10.

Pulses, at pseduo-reference frequency mf are illustrated by hatched rectangles 24a, 24g, 2411. For a better understanding of the drawing, the width of those pulses has been exaggerated.

When 24a is, for example, applied to the base of transistor l2, capacitor 15 is rapidly discharged. Then, it is recharged to the time of the next pulse 24b applied thereto.

The curve 22a, which illustrates the charge variation of 15 according to the relation:

The other curves 22b-22h are similar to 22a.

The curve 23a would illustrate the charge curve of 15 if pulses at frequency f were applied to the base of 12 instead of pulses of frequency mf Pulses at analysis frequency f,,, which are applied to the gate of transistor 16, are illustrated by dotted rectangles 25a and 25b.

The voltage, which is stored in 17, is the same as across capacitor 15 when the analysis pulse occurs.

Voltage V,. across 17 varies as indicated by the lower curve shown in FIG. 3. Between two successive storages, that voltage naturally decreases slightly, however, that is not disturbing because, when f and f are synchronized (i.e., iff is rigorously equal to f the curve illustrating the variation of V versus time involves a DC component, which is proportional to a fixed phase differencebetween reference pulses and analysis pulses, and also components at frequency f,; and harmonic frequencies thereof. The latter are eliminated by filter 19.

Before synchronization is achieved,-there is a difference AF between f,, and f Af having the maximum value (AF/N). For simplification, it is assumed that f,, (f Af) and that (l/mf r) is small enough to permit to an v t beingthe occurrence time for 25a,

when 25b occurs, and so on up to Thus V may be regarded as a signal at frequency f,; phase modulated at frequency Af. The phase of V is written: 2 1r Aft (b If the loop is closed, voltage (V,.),, applied to input lb of VCO 1 (FIG. 1), causes F to decrease as well as )2, and, consequently, Af=f,, f,, is also decreasing.

After a sequence of analysis pulses, Af tends to be come zero and only a constant phase difference corresponding to a continuous quasifixed voltage V is still existing as shown in the lower portion of FIG. 3.

It is to be noted that, beforesynchronization has been reached, voltage V varies according to a law as a function of time, first with a frequency Af, then with more and more low frequencies. The maximum frequency is equal to (AF/M AF being the frequency comparator step and l/N,,,,-,, being the lowest division ratio used in this synthesizer. Thus, filter 19, as shown in FIG. 1, has to pass that frequency which defines its cutoff frequency limit.

It is still to be noted that dividing the time interval (l/f into m equal intervals (l/mf has no effect on the frequency of the phenomena as far ascapacitor 17 and the following components are concerned.

Therefore, the open loop gain may be kept at a very high quasiconstant value, for any value of voltage V across 17, after synchronization has been reached.

Pulse shaper of FIG. 2

The width t of pulses 24a, 24b, 24c 24g, 2411, as shown in FIG. 3, is basically determined by the characteristics of the shaper 9 shown in FIG. 1. As soon as one of those pulses (for example 24a) is applied to the base of transistor 12, capacitor is discharged through the relatively low resistance of its emitter-collector path,

FIG. 1, may advantageously be replaced by the circuit of FIG. 2.

In FIG. 2, stable oscillator 8 (actually a square wave generator) produces rectangular signals at a highly stabilized frequency F and divider 7 provides f from an output 7a, and from another output 7c pulses at division ratio 1/v are available.

Output 712 is connected to pulse input h of flip-flop 21, and reset input 0 of 21 is connected from the output of stable oscillator 8.

It is assumed that flip-flop 21 changes its condition when the level at input h changes from 1"to 0.

' Such a condition change is then produced at times spaced by (M/m) (I/F since output 7b of 7 corresponds to a division ratio m/M.

Each occurrence of a pulse trailing edge from output 7b is substantially synchronized with a pulse leading edge of signals at frequency F applied to input c of 21. When c is turned to level 1, the flip-flop condition change occurs and output Q of 21 is at level l until input 0 is turned to level 0 again.

Thus output Q generates pulses at frequency with a width a little less than l/2F If that width is too short, the input 0 of 21 may be, in certain cases, taken from 70. As a consequence, pulses from output Q have the same frequency as previously,

within a time t,,. It is important that t be substantially 6 but a width (v/2F While the principles of the present invention have been hereabove described in relation with a specific embodiment, it will be clearly understood that the said description has only been made by way of example and is not intended to limit the scope of the invention.

What is claimed is:

1. A frequency synthesizer comprising:

a controllable frequency oscillator having an output a divider by N responsive to said F to produce a signal FA f u N as analysis pulses;

a stable source of reference pulses F and divider means responsive thereto to divide said F by M to produce said means also producing shaped pulses a pseudo-reference signal, where m is an integer representing a predetermined phase sampling frequency multiplier;

a frequency comparator connected to compare said analysis pulses f and said pseudo-reference pulses f,, to produce a first error signal as a function of [f f,,[ and for applying said first error signal to said controllable oscillator to modify said frequency F up to a point at which [F Nf,,l =i AF, said Af being a predetermined frequency error signal;

and a sampling phase comparator connected to compare said shaped pseudo-reference pulse signals and said analysis pulses to produce a second error signal as a function of the phase difference of said f and f, pulses, said error signal being also applied to said controllable oscillator in a sense tending to reduce said second error signal to zero.

2. Apparatus according to claim 1 in which said sampling phase comparator comprises a saw-tooth generator including a resistor of value p, a serially connected capacitor of value C, a DC source applied across said serially connected resistor and capacitor, and a switching element controlled by said pulses mf to substan tially short-circuit said capacitor once each l/mf period to generate a recurring saw-tooth wave of amplitude E /mf p c comprising the signal actually compared with said f A signal in said sampling phase comparator.

3. Apparatus defined in claim 2, further defined in that the individual saw-tooth waves of said recurring saw-tooth wave are spaced by an interval 1 and pulse shaping means connected to drive said switching element are provided, said pulse shaping means providing pulses of duration t,, spaced by said l/mf period, said t,, being longer than the discharge time of said capacitor through said switching element.

4. Apparatus according to claim 1 including circuit means responsive to said F pulse signal for producing said f and mf pulses synchronous said F pulses.

5. Apparatus according to claim 4 in which said circuit means responsive to said F signal comprises a flipflop having triggering and reset inputs and a frequency divider circuit, said triggering input being connected from said divider output delivering pulses at mF /M and said reset input being connected from an output of said divider delivering pulses at a division ratio V, said flip-flop generating said pseudo-reference pulses at frequency mf and of duration 

1. A frequency synthesizer comprising: a controllable frequency oscillator having an output FA; a divider by N responsive to said FA to produce a signal
 2. Apparatus according to claim 1 in which said sampling phase comparator comprises a saw-tooth generator including a resistor of value Rho , a serially connected capacitor of value C, a DC source applied across said serially connected resistor and capacitor, and a switching element controlled by said pulses mfB, to substantially short-circuit said capacitor once each 1/mfB period to generate a recurring saw-tooth wave of amplitude Eo/mfB Rho c comprising the signal actually compared with said fA signal in said sampling phase comparator.
 3. Apparatus defined in claim 2, further defined in that the individual saw-tooth waves of said recurring saw-tooth wave are spaced by an interval ta, and pulse shaping means connected to drive said switching element are provided, said pulse shaping means providing pulses of duration ta spaced by said 1/mfB period, said ta being longer than the discharge time of said capacitor through said switching element.
 4. Apparatus according to claim 1 including circuit means responsive to said FB pulse signal for producing said fB and mfB pulses synchronous said FB pulses.
 5. Apparatus according to claim 4 in which said circuit means responsive to said FB signal comprises a flip-flop having triggering and reset inputs and a frequency divider circuit, said triggering input being connected from said divider output delivering pulses at mFB/M and said reset input being connected from an output of said divider delivering pulses at a division ratio V, said flip-flop generating said pseudo-reference pulses at frequency mfB and of duration 